Image processing is increasingly being used for optical character recognition, machine vision, military targeting and many other applications. In image processing systems and methods, an array of image data, arranged in a plurality of rows and columns, is typically compared to a template corresponding to a known or desired pattern. Pattern recognition typically requires massive data processing which increases proportionally with the number of image data points or pixels in the image data array. The number of pixels also increases proportionally to an increase in the quality of verification of specific patterns. Thus, high speed image processing systems and methods are needed which can handle high resolution images in real time.
Image processing systems and methods have typically been implemented using either high speed general purpose data processors or specialized image processing architectures. Unfortunately, imaging systems and methods implemented on general purpose data processors are flexible but slow. Conversely, image processing systems and methods implemented using specialized architecture tend to be fast but inflexible.
In particular, image processing systems and methods have been implemented in software for general purpose data processors. In order to reduce computational complexity, these systems and methods typically require preprocessing of the image for feature extraction that includes geometric edge detection, edge thinning, compression or other characteristics. This preprocessing produces a loss of significant information from the original image, thus resulting in a decrease in performance for many pattern matching applications. Moreover, template matching for large size patterns on general purpose data processors is extremely time consuming, thereby rendering general purpose processors unacceptable for use in applications requiring pattern recognition and comparison at near millisecond rates.
In order to solve this speed problem, specialized architectures have been developed for image processing. These specialized architectures, when implemented in hardware, typically use a plurality, and often a large number, of processing elements which are interconnected in an array of rows and columns to correspond to the rows and columns of the image data. Because the image data is processed in parallel, high speed processing is possible. Unfortunately, such specialized architectures sacrifice flexibility in the quest for obtaining high speed processing. For example, the organization of the interconnected processing elements into rows and columns is typically fixed so that it is difficult to process images having an arbitrary number of rows and columns. Inter-processing element connections and control connections also become increasingly complex as the number of processing elements increases. Moreover, since such specialized architecture is typically designed to process images of a predetermined number of rows and columns, it is difficult to expand the specialized architecture to add necessary rows and columns. Finally, when using large numbers of processing elements, a single processing element may sometimes be defective. Since many processing elements are typically formed in a single integrated circuit chip, it is difficult to substitute a working processing element for a defective processing element. Thus, the chip may need to be discarded.